The present invention relates to a method for fabricating a semiconductor device, and more particularly, to a method for fabricating a nonvolatile memory device.
Recently, research on high-integration memory device technology has been actively conducted to develop high capacity memory devices which can electrically program and erase, and store a large amount of data. However, if the design rule is decreased for high-integration, the channel length of a device may shorten, causing the threshold voltage (Vt) to decrease.
Thus, the doping concentration level of threshold voltage adjusting ions has to be increased to compensate the lowered threshold voltage. However, the increased doping concentration level of the ions implanted in the substrate may cause an increased electric field between source and drain, increased junction leakage current, and a short channel effect (SCE) inducing drain induced barrier lowering (DIBL).
The most basic method for reducing a short channel effect is to reduce a substrate doping concentration level or lengthen the channel length.
FIG. 1 illustrates a top view of a typical nonvolatile memory device. FIG. 2 illustrates a cross-sectional view of the nonvolatile memory device shown in FIG. 1 in accordance with a line A-A′. FIG. 3 illustrates a cross-sectional view of the nonvolatile memory device shown in FIG. 1 in accordance with a line B-B′.
Referring to FIG. 1, a plurality of isolation structures 11 are formed in a substrate 10 with a uniform spacing distance along one direction. Control gates 15 are formed in a perpendicular direction to the isolation structures 11.
The control gates 15 are formed to cover floating gates 14. The floating gates 14 are formed over active regions 10A between the isolation structures 11.
The floating gates 14 are formed over the active regions 10A below the control gates 15. Also, portions of the floating gates 14 are extended over the isolation structures 11 adjacent to the active regions 10A in order to secure the coupling ratio.
Referring to FIGS. 2 and 3, a plurality of the isolation structures 11 having a trench structure are formed in the substrate 10 with a uniform spacing distance to define the active regions 10A.
The control gates 15 are formed over the substrate 10, across the active regions 10A. A tunnel oxide-based layer 12 and the floating gates 14 are stacked over the active regions 10A below the control gates 15 and portions of the adjacent isolation structures 11. An oxide/nitride/oxide (ONO) layer 13 is formed between the floating gates 14 and the control gates 15.
The typical nonvolatile memory device includes a planar gate structure where gates configured from the floating gates 14 and the control gates 15 are formed over the planar active regions 10A.
However, an effective channel length CH1 is determined by the line width of the floating gates 14 in the typical planar gate structure. Thus, a short channel effect may increase, causing difficulty in highly integrating the nonvolatile memory device.